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Xilinx and Synopsys Announce Next Generation Flow for Platform FPGAS
SAN JOSE, Calif.--(BUSINESS WIRE)--Aug. 27, 2001--Xilinx Inc
(Nasdaq:XLNX), the leading supplier of high-density FPGA devices, and
Synopsys Inc. (Nasdaq:SNPS), the technology leader for complex IC
design, today announced an extended flow for high-end FPGA design.
This advanced flow adds time-saving verification tools: Synopsys
LEDA® RTL rule checking, PrimeTime® static timing analysis, and
Formality® formal verification to the existing flow of Synopsys
VCS(TM) or Scirocco(TM) for simulation, Synopsys FPGA Compiler II(TM)
for synthesis, and the Xilinx Integrated Software Environment (ISE)
4.1i. This flow was designed to reduce development time while helping
to ensure that products meet specifications when realized with
Xilinx® Virtex®-II Platform FPGAs.
``With the Virtex-II family, we've extended the range of possible
applications for FPGAs,'' said Rick Sevcik, senior vice president and
general manager, Xilinx Inc. ``To get these larger, more complex FPGA
designs done on time, designers need sophisticated tools that can
assure the design will work before they get it into the lab. Our
collaboration with Synopsys to integrate the industry's more powerful
formal verification tool offers ASIC-level capabilities to FPGA
designers.''
The new FPGA flow enables designers to use tools and strategies
previously only available for ASICs and is the most comprehensive
support available for today's high-performance Platform FPGAs such as
Xilinx Virtex II. Designers create a specification in VHDL or Verilog,
and Synopsys LEDA checks HDL code for good workmanship, correctness
and performance, applying a Virtex-II rule set jointly developed with
Xilinx. This gives the designer the opportunity to fix problems up
front where they are least costly. The RTL is then simulated using a
high-speed simulator such as Synopsys VCS or Scirocco. Next, the
design is synthesized with Synopsys FPGA Compiler II, which optimizes
the high-level logic description into the advanced Virtex-II
architecture. The implementation is completed by the fast Xilinx ISE
4.1 software.
Once implemented, Virtex-II designers can save valuable
development time by performing static timing and functional
verification on the design before testing it in the lab. Xilinx
supplies scripts and libraries to enable the use of PrimeTime and
Formality, proven ASIC verification tools. PrimeTime statically
analyzes and verifies the post-layout timing of the Virtex-II device
and provides comprehensive feedback to the designer using time-saving
features such as bottleneck-and mode-analysis. Formality uses formal
mathematical techniques to quickly ensure that the design is
functionally equivalent to the RTL specification. In this way,
designers save time and also verify their Virtex-II Platform FPGAs
much more comprehensively than ever before.
``We have extended Synopsys' synthesis and high-speed simulation
flow for FPGAs, leveraging our market-leading verification solutions
used in the ASIC flow today,'' stated Antun Domic, senior vice
president and general manager of Synopsys' Nanometer Analysis and Test
Business Unit. ``Making these advanced capabilities available to FPGA
designers enables them to address complex verification challenges with
ease and greater efficiency.''
Availability
All Synopsys products are available now. For more information
visit the Synopsys web site at www.synopsys.com. The Xilinx design
rules for the Synopsys LEDA HDL Checker can be downloaded from:
www.synopsys.com/products/leda/leda.html.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View,
California, creates leading electronic design automation (EDA) tools
for the global electronics market. The company delivers advanced
design technologies and solutions to developers of complex integrated
circuits, electronic systems, and systems on a chip. Synopsys also
provides consulting and support services to simplify the overall IC
design process and accelerate time to market for its customers. Visit
Synopsys at http://www.synopsys.com.
About Xilinx
Xilinx is the leading supplier of complete programmable logic
solutions, including advanced integrated circuits, software design
tools, predefined system functions delivered as cores, and
unparalleled field engineering support. Founded in 1984 and
headquarters in San Jose, Calif., Xilinx invented field programmable
gate arrays (FPGA) and fulfills more than half of the world demand for
these devices today. Xilinx solutions enable customers to
significantly reduce the time required to develop products for the
computer, peripheral, telecommunication, networking, industrial
control, instrumentation, high-reliability/military, and consumer
markets. For more information, visit the Xilinx web site at
www.xilinx.com.
Note to Editors: Synopsys, PrimeTime, Formality and LEDA are
registered trademarks and VCS, Scirocco, FPGA Compiler II are
trademarks of Synopsys, Inc. All other trademarks or registered
trademarks mentioned in this release are the intellectual property of
their respective owners.
Contact:
Synopsys, Inc.
Robert Smith, 650/584-1261
rsmith@synopsys.com
or
KVO Public Relations
Christina Castillo, 503/221-2355
christina_castillo@kvo.com
or
Xilinx, Inc.
Ann Duft, 408/879-4726
publicrelations@xilinx.com
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